module dispatch_cond(
    input [27:0] instr,
    output is_dp,
    output is_lsx,
    output is_mul,
    output is_ls,
    output is_ext,
    output is_lsm,
    output is_b,
    output is_mrs,
    output is_msr,
    output is_bx,
    output is_swi,
    output undefined
);
reg [11:0] iclass;
assign undefined = iclass[0];
assign is_dp = iclass[1];
assign is_lsx = iclass[2];
assign is_mul = iclass[3];
assign is_ls = iclass[4];
assign is_ext = iclass[5];
assign is_lsm = iclass[6];
assign is_b = iclass[7];
assign is_mrs = iclass[8];
assign is_msr = iclass[9];
assign is_bx = iclass[10];
assign is_swi = iclass[11];
always @* begin
    casez (instr)
        28'b00000??0???????????????0????: iclass = 1<<1;
        28'b00001??0???????????????0????: iclass = 1<<1;
        28'b00011??0???????????????0????: iclass = 1<<1;
        28'b000????1???????????????0????: iclass = 1<<1;
        28'b00000??0????????????0??1????: iclass = 1<<1;
        28'b00001??0????????????0??1????: iclass = 1<<1;
        28'b00011??0????????????0??1????: iclass = 1<<1;
        28'b000????1????????????0??1????: iclass = 1<<1;
        28'b00100??0????????????????????: iclass = 1<<1;
        28'b00101??0????????????????????: iclass = 1<<1;
        28'b00111??0????????????????????: iclass = 1<<1;
        28'b001????1????????????????????: iclass = 1<<1;
        28'b000?????????????????1011????: iclass = 1<<2;
        28'b000?????????????????1101????: iclass = 1<<2;
        28'b000?????????????????1111????: iclass = 1<<2;
        28'b000000??????????????1001????: iclass = 1<<3;
        28'b00001???????????????1001????: iclass = 1<<3;
        28'b010?????????????????????????: iclass = 1<<4;
        28'b011????????????????????0????: iclass = 1<<4;
        28'b01101?11??????????000111????: iclass = 1<<5;
        28'b01101??0??????????000111????: iclass = 1<<5;
        28'b100?????????????????????????: iclass = 1<<6;
        28'b101?????????????????????????: iclass = 1<<7;
        28'b00010?001111????000000000000: iclass = 1<<8;
        28'b00010?10????111100000000????: iclass = 1<<9;
        28'b00110?10????1111????????????: iclass = 1<<9;
        28'b0001001011111111111100?1????: iclass = 1<<10;
        28'b1111????????????????????????: iclass = 1<<11;
        default: iclass = 1;
    endcase
end
endmodule
